Coarse Grain Reconfigurable Architecture

A Coarse Grain Reconfigurable Architecture (CGRA), is a type of processor architecture that can be reconfigured at runtime, much like an FPGA. However, where an FPGA is configured at the gate level, a CGRA is configurable at the Function Unit (FU) level. This keeps a lot of the flexibility of an FPGA to construct compute platforms specialized for a given application, but has a smaller configuration overhead.

Conceptual architecture overview

A CGRA can be very energy efficient, as it enables the creation of a spatial layout for an application. That means the FUs are configured once, and execute (as much as possible) the same instruction, while the data flows through the compute network. The major energy advantage is that the FU computes the exact same instruction everytime, reducing accesses to the instruction memory and keeping the toggling of control signals to a minimum.

Furthermore, by splitting the Instruction Decode (ID) from the FUs, it is possible to group the FUs into SIMD and VLIW like structures. In general SIMD exploits data level parallelism (DLP), while VLIW exploits instruction level parallelism (ILP). How much DLP and ILP is present heavily depends on each particular application. Because a CGRA can be reconfigured, the right mix of SIMD and VLIW structures can be configured for each application to achieve the highest energy efficiency.

In today's processors, memory is becoming one of the main sources of energy usage. One solution people are working on is Near Memory Computation, which moves certain compute logic closer to the memory, making memory a more central part of a processing architecture, as opposed to the traditional model where the compute (logic) is central. Instead of moving small, selected parts of the compute towards the memory, a CGRA architecture enables a more interesting option. By reconfiguring the FUs around the memory that hold the data of interest, it can bring the required compute right next to the memory. In this sense a CGRA architecture is the ultimate Near Memory Compute architecture, as it can truly bring the computation to the data, instead of the other way around.

Our Mission

We of the Electronic Systems group of Eindhoven University of Technology (TU/e) strive to design an Energy Efficient CGRA architecture, with accompanying tool support. In particular the architecture should be targeted at signal processing in the EEG and ECG domains, although there are many other domains of interest, such as: vision and image processing, telecommunications, machine learning and linear algebra. In case you are interested in our work, please do not hesitate to contact us at {m.wijtvliet, l.j.w.waeijen} If you are a student looking for an internship or master project, please contact us as well.